View LC7233N_293632.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number:ENN*4117
CMOS IC
LC7233N
Single-Chip PLL and Microcontroller with LCD Driver
Preliminary Overview
The LC7233N is a single-chip microcontroller that incorporates a 0.5 to 150 MHz phase-locked loop (PLL) and a liquid-crystal display (LCD) driver, making it ideal for digital tuners. It has a large number of input/output ports and a frequency measurement circuit. The LC7233N features on-chip RAM and ROM, a programmable high-speed divider, a 6-bit analog-to-digital converter and a low-voltage detection reset circuit. The LC7233N operates from a 5 V supply and is available in 64-pin QIPs.
Package Dimensions
unit:mm 3159-QIP64E
[LC7233N]
17.2 1.0
1.6 1.0
0.8
14.0 0.35 33
1.6 1.0
0.15 32
48 49
17.2
14.0 0.8
Features
* 0.5 to 150 MHz phase-locked loop. * LCD driver. * 6-bit analog-to-digital converter. * Two 8-bit PWM digital-to-analog converters. * Two 4-bit input ports. * Two 4-bit input/output ports. * 6-bit keypad matrix scan output port. * 2-bit open-drain high-voltage output port. * 23 mask-selectable output drivers. * 20-bit universal counter. * 4096 x 16-bit program ROM (001H to FFFH user addressable memory). * 256 x 4-bit data RAM. * Low-voltage detection reset circuit. * Programmable high-speed divider. * Single-word instructions. * Four-level stack. * PLL-unlocked flip-flop. * Timer flip-flop. * External interrupt. * Programmable watchdog interrupt address. * Standby mode. * CPU operates down to 3.5 V and retains data down to 1.3 V. * 5 V supply. * 64-pin QIP.
1.0
17 1 16
3.0max
64
0.1 2.7
15.6
0.8
SANYO : QIP64E
Pin Assignment
Top view
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80101TN (KT)/3062JIN No.4117-1/12
LC7233N
Block Diagram
No.4117-2/12
LC7233N
Pin Description
Number 1 Name XIN Crystal oscillator connections 64 2 63 XOUT TEST2 TEST1 Equivalent circuit Description
Test pins
3
PG3/INT
Multiplexed input port G bit and interrupt request input
4 to 6
PG2 to PG0
Input port G
7, 8
PH1, PH0
Output port H
9 to 12
PF3 to PF0
Input/output port F
13 to 16
PE3 to PE0
Input/output port E
17, 18
PC1, PC0
Output port C
19 to 22
PB3 to PB0
Output port B
23 to 26
PA3 to PA0
Input port A
27 to 49
S23 to S1
LCD segment outputs
Continued on next page. No.4117-3/12
LC7233N
Continued from preceding page.
Number Name Equivalent circuit Description
50, 51
COM2, COM1
LCD common driver outputs
52
HOLD
Hold-mode control input
55
SNS
Power-fail detect
53
ADI
A/D converter input
54
HCTR
Univarsal counter input
56
VDD
5 V supply
57
FMIN
FM VCO input
58
AMIN
AM VCO input
59
VSS
Ground
60
EO
Phase comparator output
61
AIN
Analog input
62
AOUT
Analog output
No.4117-4/12
LC7233N Specifications
Absolute Maximum Ratings
Parameter Supply voltage Port G, HOLD, ADI and SNS input voltage Input voltage (other inputs) Port H and AOUT output voltage Output voltage (all other outputs) Port H output current Ports E and F output current Ports B and C output current AOUT output current Allowable power dissipation Operating temperature Storage temperature Symbol VDD VI1 VI2 VO1 VO2 IO1 IO2 IO3 IO4 Pd max Topr Tstg Conditions Ratings - 0.3 to+6.5 - 0.3 to+13.0
- 0.3 to VDD+0.3 - 0.3 to+15.0 - 0.3 to VDD+0.3 0 to 5 0 to 3 0 to 1 0 to 2
Unit V V V V V mA mA mA mA mW C C
400 - 40 to +85 - 45 to +125
Recommended Operating Conditions at Ta = 25C
Parameter Supply voltage Supply voltage range (PLL and CPU) Supply voltage range (CPU) Supply voltage range for data retention Symbol VDD VDD1 VDD2 VDD3 Conditions Ratings 5 4.5 to 5.5 3.5 to 5.5 1.3 to 5.5 Unit V V V V
Electrical Characteristics at Ta = -40 to +85C, VDD = 3.5 to 5.5V, unless otherwise noted
Parameter Supply current Hold-mode supply current Symbol IDD1 IDD2 Conditions fI=130MHz, VDD=4.5 to 5.5V PLL halted, tcyc=2.67s, VDD=3.5 to 5.5V PLL halted, tcyc=13.33s, VDD=3.5 to 5.5V PLL halted, tcyc=40.00s, VDD=3.5 to 5.5V Standby-mode supply current Port A and PG3/INT low-level input voltage Ports E and F low-level input voltage PG0 to PG2 low-level input voltage HOLD low-level input voltage SNS low-level input voltage Port A high-level input voltage Ports E and F high-level input voltage PG0 to PG2 high-level input voltage HOLD and PG3/INT high-level input voltage SNS high-level input voltage XIN rms input amplitude FMIN rms input amplitude AMIN rms input amplitude HCTR rms input amplitude PG3/INT input hysteresis width ADI input voltage Port A input voltage Standby threshold voltage XIN input frequency FMIN input frequency AMIN input frequency (low range) AMIN input frequency (high range) HCTR input frequency SNS reject pulsewidth Ports A, E and F low-level input current AIN low-level input current FMIN, AMIN and HCTR low-level input current IDD3 VIL1 VIL2 VIL3 VIL4 VIL5 VIH1 VIH2 VIH3 VIH4 VIH5 VI1 VI2 VI3 VI4 VHYS VI5 VIF VDET fI1 fI2 fI3 fI4 fI5 Prej IIL1 IIL2 IIL3 Port A is high impedance. Port A has RPD. 2.7 VI=0.5 to 1.5 V VI=0.1 to 1.5 V, VDD=4.5 to 5.5 V VI=0.15 to 1.5 V, VDD=4.5 to 5.5 V VI=0.1 to 1.5 V, VDD=4.5 to 5.5 V VI=0.1 to 1.5 V, VDD=4.5 to 5.5 V VI=0.1 to 1.5 V, VDD=4.5 to 5.5 V Ports E and F are high impedance. Port A has no RPD. VI=VSS VI=VSS VI=VSS 4 0.01 10 4.0 10 10 0.5 2 0.4 3.0 4.5
VDD=5.5V, oscillator halted, Ta=25C VDD=2.5V, oscillator halted, Ta=25C
Ratings min typ 15 1.5 1.0 0.7 5 1 0 0 0 0 0 0.6VDD 0.7VDD 0.7VDD 0.8VDD 2.7 0.5 0.1 0.1 0.1 0.1VDD 0 VDD
0.05VDD
max 20
Unit mA mA
A V V V V V V V V V V V V V V V V V V MHz MHz MHz MHz MHz s A nA A
0.2VDD 0.3VDD 0.3VDD 0.4VDD 1.3 VDD VDD 8.0 8.0 8.0 1.5 1.5 1.5 1.5
3.3 5.0 130 150 10.0 40 12.0 50 3 10.0 30
Continued on next page. No.4117-5/12
LC7233N
Continued from preceding page.
Parameter HOLD, ADI, SNS and port G low-level input current XIN low-level input current Ports A, E and F high-level input current Port A high-level input current AIN high-level input current FMIN, AMIN and HCTR high-level input current HOLD, ADI, SNS and port G high-level input current XIN high-level input current Ports B and C low-level output voltage Ports E and F low-level output voltage Port H low-level output voltage AOUT low-level output voltage COM1 and COM2 low-level output voltage EO low-level output voltage S1 to S23 low-level output voltage XOUT low-level output voltage COM1 and COM2 mid-level output voltage Ports B and C high-level output voltage Ports E and F high-level output voltage COM1 and COM2 high-level output voltage EO high-level output voltage S1 to S23 high-level output voltage XOUT high-level output voltage Ports B, C, E and F low-level output leakage current EO low-level output leakage current Ports B, C, E and F high-level output leakage current Port H high-level output leakage current AOUT high-level output leakage current EO high-level output leakage current A/D converter error Port A pull-down resistance Symbol IIL4 IIL5 IIH1 IIH2 IIH3 IIH4 IIH5 IIH6 VOL1 VOL2 VOL3 VOL4 VOL5 VOL6 VOL7 VOL8 VM1 VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 IOFFL1 IOFFL2 IOFFH1 IOFFH2 IOFFH3 IOFFH4 RPD VI=VSS VI=VSS Ports E and F are high impedance. Port A has no RPD. VI=VDD VI=VDD=5.0V, Port A has RPD. VI=VDD VI=VDD=5.0V VI=5.5V VI=VDD=5.0V IO=50A IO=1 mA IO=5 mA IO=5 mA, VAIN=1.3V IO=25A IO=500A IO=0.1mA IO=200A VDD=5V, IO=20A IO=1 mA IO=1 mA IO=25A IO=500A IO=- 0.1mA IO=200A VO=VSS VO=VSS VO=VDD VO=13V VO=13V VO=VDD VDD=4.5 to 5.5V VDD=5V - 1/2 75 100 0.01 0.01 2.0 2.5 0.3 0.5 2 0.5 0.75 (150) 5 1.0 4 2 5 Conditions Ratings min typ max 3 15 3 50 0.01 10 10.0 30 3 15 2.0 1 2.0 (400) 0.5 0.75 1 1 1 3.0
VDD- 2.0 VDD- 1.0 VDD- 0.5 VDD- 1.0
VDD- 0.75
Unit A A A A nA A A A V V V V V V V V V V V V V V V 3 A A A A A nA lsb k
VDD- 0.5 VDD- 0.3
VDD- 1.0 VDD- 1.0 VDD- 1.0
10.0 3 5 1 10.0 1/2 200
Test Circuits
Hold mode
Notes 1. Ports E and F are selected as output ports. 2. Ports A to H, S1 to S23, COM1 and COM2 are open.
No.4117-6/12
LC7233N
Standby mode
Note Ports A to H, S1 to S23, COM1 and COM2 are open.
Functional Description
LCD Driver The LC7233N can drive LCD segments. The LCP and LCD instructions transfer data to the LCD outputs. The LCD instruction transfers data directly to the LCD outputs. The LCP instruction converts data to 7-segment format before transfer to the outputs. S1 to S23 are the driver outputs. The LCD frame rate is 100 Hz with a 50% duty cycle. After reset or power-up, a blank signal is present on all outputs. In standby mode, all outputs are LOW. They can be used as generalpurpose outputs if the appropriate mask option is selected. COM1 and COM2 are the LCD common driver outputs. Output drive is 50% duty with 50% bias. Upon reset or after power-up, the normal drive signals are present on these outputs. In standby mode, all outputs are LOW. Frequency Counter Frequency measurement is performed at the HCTR input by the 20-bit universal counter. The input frequency range is 0.4 to 12 MHz, which is used for measuring AM and FM IF frequencies. Capacitive coupling should be used. Phase-locked Loop The FMIN or AMIN input signal is divided down by a programmable divider, and then compared with the crystal frequency, which is also divided down using 14 selectable ratios. The phase difference between the two signals is measured using a phase detector and output on EO. FMIN is the input pin for the FM VCO input signal. The input frequency range is 10 to 130 MHz. Capacitive coupling should be used. AMIN is the AM VCO input. The bandwidth is adjustable in two ranges by using the PLL instruction-HIGH (2 to 40 MHz) for the SW band, and LOW (0.5 to 10 MHz), for the LW and MW bands. Capacitive coupling should be used. Input/Output Ports Port A This input port has a low switching threshold, which is used for keypad matrix inputs. Pull-down resistors for all pins are available as a mask option. Note that either all or none of the pins should have pull-down resistors. In standby mode, inputs are ignored. Ports B and C These output ports have unbalanced CMOS outputs which are used as keypad matrix scan outputs. Upon reset, outputs are set LOW, and in standby mode, outputs are high impedance. The outputs can be short-circuited. Port E The transfer direction of this input/output port is selected automatically under software control. When an input instruction (IN, TPT, or TPF) is executed, port E is configured for input operation, and an output instruction (OUT, SPB or RPB), for output operation. Upon reset, all pins become inputs. In standby mode, the output drivers are high impedance and the input signals are ignored. All bits should either be inputs or outputs. Port F The transfer direction of this input/output port is selected by the FPC instruction. Each pin of this port can be set independently to be an input or output. Upon reset, all pins become inputs. In standby mode, the output drivers are high impedance and the input signals are ignored. Port G PG0 to PG2 are inputs only. PG3/INT can be used as a standard input or as the interrupt request input. In standby mode, inputs are ignored.
No.4117-7/12
LC7233N
Port H These output ports are high-voltage, n-channel opendrain drivers, which are used for switching power supplies. Upon reset and in standby mode, outputs are high impedance. Port H can also be configured as the output of DAC1 and DAC2. A/D Converter The A/D converter is a 6-bit successive approximation type. The conversion cycle time is 1.28 ms. Full-scale output data is 3FH for an input of (63/96) x VDD. Power-fail Detection When connected to the supply, SNS is used as a powerfail detector. SNS can also be used as a standard input port. Crystal Oscillator The master crystal oscillator, which has a feedback resistor on-chip, requires only the connection of a 4.5 MHz crystal. Low-power Modes Hold mode When the hold-mode control pin, HOLD, is driven LOW and the HOLDEN (hold enable) flip-flop has previously been set by an SS instruction, the LC7233N enters hold mode. HOLD has a high-voltage input (VIH(max) = 8.0 V) which can be connected directly to the power supply. Standby mode When the LC7233N is in hold mode and HOLD is LOW, standby mode can be set by the CKSTP instruction. Test Pins Two device test pins are provided-TEST1 and TEST2. These should either be tied to VSS or left open.
Instruction Set
ADDR b B C DH DL I M N Pn r Rn () ( )n Program memory address [12 bits] Borrow Bank number [2 bits] Carry Data memory address high-order bits (row address) [2 bits] Data memory address low-order bits (column address) [4 bits] Immediate data [4 bits] Data memory address Bit position [4 bits] Port number [4 bits] General register (Bank 0 addresses 00H to 0FH) Register number [4 bits] Contents of register or memory Contents of bit N of register or memory
No.4117-8/12
Mnemonic D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Operand Notation Description Skip condition Add 0 0 0 0 0 0 0 0 Subtract 1 1 1 1 1 1 1 1 Compare 0 0 1 1 1 1 1 DH 1 0 1 DH 0 1 1 DH DL DL DL 0 0 1 DH DL Rn Rn I I (r) - (M), skip if zero (r) - (M), skip if (r) (M) (M) - I, skip if zero (M) - I, skip if (M) I
Compares the contents of r and M and skips if they are equal. Compares the contents of r and M and skips if r is greater than or equal to M. Compares the immediate data to the contents of M and skips if they are equal. Compares the contents of M with the immediate data and skips if M is greater than or equal to I.
1st
2nd
Operation
Instruction format
D15
D14
AD 0 0 0 1 1 1 1 1 1 DH DL I M (M) + I + C, skip if carry 1 0 DH DL I M (M) + I + C 0 1 DH DL I M (M) + I, skip if carry 0 0 DH DL I M (M) + I 1 1 DH DL Rn r (r) + (M) + C, skip if carry 1 0 DH DL Rn r (r) + (M) + C
Adds the contents of M to the contents of r and C and stores the result in r. Adds the contents of M to the contents of r and C and stores the result in r. Skips if a carry is generated. Adds the immediate data to the contents of M and stores the result in M. Adds the immediate data to the contents of M and stores the result in M. Skips if a carry is generated. Adds the immediate data to the contents of M and C and stores the result in M. Adds the immediate data to the contents of M and C and stores the result in M. Skips if a carry is generated.
r 0 1 DH DL Rn r (r) + (M), skip if carry
Adds the contents of M to the contents of r and stores the result in r. Skips if a carry is generated.
M
Add M to r.
0
1
0
0
0
DH
DL
Rn
r (r) + (M)
Adds the contents of M to the contents of r and stores the result in r.
ADS
r
M
Add M to r and skip if carry.
0
1
Carry
AC
r
M
Add M to r with carry.
0
1
ACS
r
M
Add M to r with carry and skip if carry.
0
1
Carry
AI
M
I
Add I to M.
0
1
AIS
M
I
Add I to M and skip if carry.
0
1
Carry
AIC
M
I
Add I to M with carry.
0
1
AICS
M
I
Add I to M with carry and skip if carry.
0
1
Carry
SU 0 0 0 1 1 1 1 1 1 DH DL 1 0 DH DL I I 0 1 DH DL I 0 0 DH DL I 1 1 DH DL Rn 1 0 DH DL Rn r (r) - (M) - b r (r) - (M) - b, skip if borrow M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow 0 1 DH DL Rn r (r) - (M), skip if borrow
r
M
Subtract M from r.
0
1
0
0
0
DH
DL
Rn
r (r) - (M), skip if carry
Subtracts the contents of M from the contents of r and stores the result in r. Subtracts the contents of M from the contents of r and stores the result in r. Skips if a borrow is generated. Subtracts the contents of M from the contents of r with borrow and stores the result in r. Subtracts the contents of M from the contents of r with borrow and stores the result in r. Skips if a borrow is generated. Subtracts the immediate data from the contents of M and stores the result in M. Subtracts the immediate data from the contents of M and stores the result in M. Skips if a borrow is generated. Subtracts the immediate data from the contents of M with borrow and stores the result in M. Subtracts the immediate data from the contents of M with borrow and stores the result in M. Skips if a borrow is generated.
SUS
r
M
Subtract M from r and skip if borrow.
0
1
Borrow
LC7233N
SB
r
M
Subtract M from r with borrow.
0
1
SBS
r
M
Subtract M from r with borrow and skip if borrow.
0
1
Borrow
SI
M
I
Subtract I from M.
0
1
SIS
M
I
Subtract I from M and skip if borrow.
0
1
Borrow
SIB
M
I
Subtract I from M with borrow.
0
1
SIBS
M
I
Subtract I from M with borrow and skip if borrow.
0
1
Borrow
SEQ
r
M
Skip if r equals M.
0
0
(r) = (M) (r) (M) (M) - I = 0 (M) I
SGE
r
M
Skip if r is greater than or equal to M.
0
0
SEQI
M
I
Skip if M equals I.
0
0
SGEI
M
I
Skip if M is greater than or equal to I.
0
0
No.4117-9/12
Continued on next page.
Continued from preceding page.
Instruction format
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mnemonic
Operand Notation Description Skip condition Logic arithmetic 1 1 1 Load and store 0
Moves the contents of M to r. Moves the contents of r to M. Moves the contents of M to the address referenced by DH and R n. Moves the contents of the memory location referenced by DH and Rn to M. Moves the contents of the memory location 2 to memory location 1. Moves the immediate data to M. Moves the contents of M to the PLL registers.
1st
2nd
Operation
D15
D14
A ND 1 0 0 0 DH DL Rn r (r) (M)
Calculates the logic-XOR of the contents of r and M, and stores the result in r.
M 1 0 DH DL I M (M) I
Calculates the logic-OR of the immediate data and the contents of M and stores the result in M.
I
AND I with M.
0
0
1
0
0
DH
DL
I
M (M) I
Calculates the logic-AND of the immediate data and the contents of M and stores the result in M.
OR
M
I
OR I with M.
0
0
EXL
r
M
Exclusive-OR M with r.
0
0
LD 0 0 0 0 0 0 Bit test 1 1 Jump and subroutine 1 0 0 0 Flag test 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 Bank select 0 1 0 0 B 0 0 0 0 0 0 0 0
BANK B
r 0 0 0 1 1 1 1 0 DH DL Rn PLLr (M) 0 1 DH DL I MI 0 0 DH DL1 DL2
[DH. DL1] [DH. DL2]
M 0 1 1 1 DH DL Rn M [DH, Rn] 0 DH DL Rn [DH, Rn] (M) 1 DH DL Rn M (r)
Load M into r.
1
0
0
0
0
DH
DL
Rn
r (M)
ST
M
r
Store r in M.
1
0
MVRD
r
M
Move M to M addressed by Rn.
1
0
MVRS
M
r
Move M addressed by Rn t o M .
1
0
MVSR
M1
M2
Move M to M .
1
0
MVI
M
I
Move I to M.
1
0
PLL
M
r
Load M to PLL registers.
1
0
TMT 0 1 1 DH DL N skip if M(N) = all 0
M
N
Test bits of M and skip if true
1
0
0
0
1
DH
DL
N
skip if M(N) = all 1
Tests the bits of memory location M specified by N. Skips if all bits are logic 1. Tests the bits of memory location M specified by N. Skips if all bits are logic 0.
All bits specified = 1 All bits specified = 0
LC7233N
TMF
M
N
Test bits of M and skip if false
1
0
JMP 0 1 1 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 N N N N N N 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ADDR (12 bits)
ADDR
Jump to address
1
0
1
ADDR (12 bits)
PC ADDR Stack (PC) + 1, PC ADDR PC stack PC stack Skip if timer F/F = 0 Skip if PLL F/F = 0
Jumps to the address specified by ADDR. Jumps to the subroutine specified by ADDR. Returns from a subroutine. Returns from a interrupt.
CAL
ADDR
Call subroutine
1
1
RT
Return from subroutine
1
1
R TI
Return from interrupt
1
1
TTM
N
Test timer flip-flop
1
1
Tests the timer flip-flop and skips if zero. Tests the PLL-unlocked flip-flop and skips if zero.
Timer F/F = 0 PLL F/F = 0
TUL
N
Test PLL flip-flop
1
1
Status register test and set
(Status register 1) N 1 Sets the bits of status register 1 specified by N. (Status register 1) N 0 Resets the bits of status register 1 specified by N. Skip if (status register 2) N = all 1 Skip if (status register 2) N = all 0
SS
N
Set status register bits
1
1
RS
N
Reset status register bits
1
1
TST
N
Test status register bits and skip if true
1
1
Tests the bits of status register 2 specified by N. Skips if all bits are 1. Tests the bits of status register 2 specified by N. Skips if all bits are 0.
All bits specified = 1 All bits specified = 0
TSF
N
Test status register bits and skip if false
1
1
BANK
B
Select bank
1
1
Selects one of four memory banks.
No.4117-10/12
Continued on next page.
Continued from preceding page.
Instruction format
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mnemonic
Operand Notation Description Skip condition Input/output 1
Loads the immediate data directly to the LCD driver. Converts the immediate data to 7-segment format using a PLA then transfers it to the LCD driver. Moves the data from input port Pn to M. Moves the contents of memory location M to port Pn. Sets the bits of port Pn specified by N to logic 1. Sets the bits of port Pn specified by N to logic 0. Tests the bits of port Pn specified by N. Skips if all bits are logic 1. Tests the bits of port Pn specified by N. Skips if all bits are logic 0. All bits specified = 1 All bits specified = 0
1st
2nd
Operation
D15
D14
LCD 1 1 1 1 1 1
Skip if (port (P)) N = all 1 Skip if (port (P)) N = all 0
M 0 0 0 1 1 1 1 Universal counter 0 0 Miscellaneous 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0
Stop clock if HOLD = 0
I 0 1 1 0 0 1 1 1 1 1 P N 0 1 0 P N 1 0 1 P N
(port (P)) N 0
Move data to LCD segments.
1 1 0 1 0 0 0 P N
(port (P)) N 1
1 DH DH DH DL P
(port (P)) M
0 DL DL P
M (port (P))
0 DIGIT
LCD (DIGIT) PLA M
0
DH
DL
DIGIT
LCD (DIGIT) M
LCP
M
I
Move 7-segment data to LCD.
1
1
IN
M
Pn
Move port data to M.
1
1
OUT
M
Pn
Move data to port.
1
1
SPB
Pn
N
Set port bits.
1
1
RPB
Pn
N
Reset port bits.
1
1
TPT 1
Pn
N
Test bits of port and skip if true.
1
1
TPF
Pn
N
Test bits of port and skip if false.
1
1
UCS 0 0 0 1 1 0 0 0 0 I
UCCW2 I
I
Set UCCW1.
0
0
0
0
0
0
1
0
0
0
0
I
UCCW1 I
Sets the universal counter flag 1. Sets the universal counter flag 2.
UCC
I
Set UCCW2.
0
0
FPC
N
Port F direction control.
0
0
1
0
0
0
0
0
0
0
0
N
FPC latch N
Defines the direction of individual pins of port F. If a bit in the port F direction register is set by FPC, the corresponding pin of port F becomes an output. Stops the processor clock if HOLD = 0 No operation
CKSTP
Stop clock.
0
0
LC7233N
NOP
No operation
0
0
No.4117-11/12
LC7233N
Mask Option
Parameter Watchdog timer (WDT) Pull-down resistors on port A (the keypad matrix input port) Instruction cycle time Yes No Yes No 2.67 s Options
Parameter Instruction cycle time S1 to S23 configuration 13.33 s 40.00 s LCD driver output port General-purpose output port Options
Development System The LC7223N development environment is shown in the following figure. It uses an LC72EV32 evaluation chip mounted on a TB-72EV32 target board and a multifunc-
tional emulator (RE32), which is controlled by a personal computer, to provide full debugging facilities.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2001. Specifications and information herein are subject to change without notice.
PS No.4117-12/12

▲Up To Search▲

Price & Availability of LC7233N

	To Download LC7233N Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .